drjobs Senior ASIC Integration and CAD Engineer

Senior ASIC Integration and CAD Engineer

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1 Vacancy
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Job Location drjobs

Santa Clara County, CA - USA

Monthly Salary drjobs

Not Disclosed

drjobs

Salary Not Disclosed

Vacancy

1 Vacancy

Job Description

Your Career

As an ASIC Integration and CAD Engineer you will ensure that the ASICs in our groundbreaking nextgeneration firewall products meet or exceed industryleading requirements for performance reliability and power efficiency.  You will integrate thirdparty IPs and PANW designs at the subsystem and top levels.  You will guide the design team on strategies for clocks resets and synchronization.  You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning closing timing validating constraints and optimizing power consumption.

Your Impact

  • Integrate PANW designs at the subsystem and top levels ensuring robust solutions for clocks resets feedthroughs and DFT.

  • Integrate RAMs CAMs custom IPs and IO pads throughout the design hierarchy.

  • Collaborate with external ASIC vendors to define optimal floorplans power grids clocking strategies and custom routing.

  • Guide internal RTL designers in closing timing reducing congestion optimizing power consumption and validating constraints.


Qualifications :

Your Experience 

  • BS in EE CE or CS required.  MSEE preferred.

  • Minimum 5 years experience in ASIC integration and front end design.

  • Demonstrated success in taking ASICs to mass production.

  • Expertise in synthesis and static timing analysis.

  • Required strengths:

    • Integrating RTL modules memories custom IPs and IOs at multiple hierarchical levels.

    • Implementing integration RTL in SystemVerilog

    • Good understanding of global clocking and reset schemes

    • Defining and validating timing constraints and exceptions.

    • Closing timing with static timing analysis and verifying clock domain crossing paths.

  • Preferred experience:

    • Creating automated flows for toplevel integration.

    • Physical synthesis with Fusion Compiler.

    • RTL quality checks: Lint CDC RDC Xverification.

    • Physical design for networking ASICs with wide data paths and memorydominant floorplans.

    • Advising designers on optimizing congestion and power dissipation.

  •  
  • Skilled in writing powerful modular and scalable programs in Python / Perl / Unix shell to automate integration and physical design.

  • Demonstrated ownership and independence in planning managing multiple priorities driving vendors and reporting status

  • Strong leadership collaboration and communication skills


Remote Work :

No


Employment Type :

Fulltime

Employment Type

Full-time

Company Industry

Department / Functional Area

Engineering

About Company

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