Hardware Developer
Hardware Developer
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1 Vacancy
Job Description
JD :
Be part of a dynamic and skilled IBM Research team developing test chip design enablement for the worlds most advanced semiconductor technologies. This role will be responsible for multiple aspects of our Research test chip design and tape out activities which include kerf/scribe development and data processing scripts and algorithms for testchip assembly and tape out operations and logistics. Develop layouts for optical marks for reticle frame (also referred to as kerf or scribe) using both design automation and manual layout per specified requirements using industry standard (EDA)
Be part of a dynamic and skilled IBM Research team developing test chip design enablement for the worlds most advanced semiconductor technologies. This role will be responsible for multiple aspects of our Research test chip design and tape out activities which include kerf/scribe development and data processing scripts and algorithms for testchip assembly and tape out operations and logistics. Develop layouts for optical marks for reticle frame (also referred to as kerf or scribe) using both design automation and manual layout per specified requirements using industry standard (EDA)
1. tools such as Cadence Virtuoso Design Environment and SKILL code. Specified layout structures will include nonelectrical optical marks for alignment overlay thin film measurement and more rather than working circuitry. Develop custom parametrized cells (pcells) for use in design automation for frame structures. Ensure that designed layouts pass required Design Rule Checks (DRC) and meet customer requirements. In addition develop and execute automated scripts to assist with test chip assembly design verification and reticle tape out operations. Close and frequent cooperation with development patterning photolithography metrology process integration and enablement engineers will be required.
Job Duties: Example tweak as needed:
Develop kerf structure layout using design automation per specified requirements using industry standard (EDA) tools including Cadence Virtuoso Design Environment and SKILL code.
Develop manual layout kerf structures per specified requirements using industry standard (EDA) tools including Cadence Virtuoso Design Environment.
Interpret Design Rules and Macro Specifications. Work closely with photolithography metrology and process integration and enablement engineer to develop kerf optical structures that meets the tool and technology requirements.
Debug and solve problems in a team environment..
Basic Skills clearances and other elements required in order of importance and number of years experience where applicable in each skill:
Strong experience using VLSI EDA tools Cadence Virtuoso Synopsys ICVWB or similar layout design tool at least 3 years.
Experience with software engineering automation and scripting (i.e. Python Cadence Skill programming language and/or shell scripting on a Linux platform) at least 2 years.
Basic understanding of physical layout technology ground rules and semiconductor processing.
Ability to debug errors and solve problems.
Ability to work in a team environment.
Fluent English (both verbal and written) and strong communication skills.
Preferred location is Albany NY. Alternative location: remote location.
Other Skills Desired Years in each skill where applicable:
1) Preferred: Experience with advanced submicron semiconductor technology nodes.
2) Preferred: Experienced user of Synopsys ICV DRC checking tool.
3) Preferred: Experience with Cadence SKILL programming language for pcell development & design automation
4) Preferred: Experience with software engineering automation and scripting (e.g. Python and/or shell scripting on a Linux platform)
5) Preferred: Familiarity with optical scribe (frame/kerf) mask structures used in metrology & photolithography.
Employment Type
Full Time
