ASIC RTL Design Engineer
ASIC RTL Design Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
Architecture and microarchitecture of System on a Chip (SOC) subsystems Intellectual Property Functional Blocks (IPs) subIPs modules and library components
- Digital design using System Verilog and/or Verilog RTL RTL generators (in Python) and/or highlevel synthesis (HLS). RTL integration of SoC subsystems IPs subIPs modules and library components
- SoClevel integration
- Support mapping of RTL on Zebu and HAPS for IP bringup and E2E validation
- Design for low power and power intent design using (UPF)
- Constraint development synthesis timing closure and optimization of the design
- Code quality checks including but not limited to Linting Clock Domain Crossing Reset Domain Crossing
- Debug and bug fixes
Employment Type
Full Time
