Contract Hardware Engineer Mid
Contract Hardware Engineer Mid
Posted on :
04-12-2024
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1 Vacancy
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Posted on :
04-12-2024
Job Description
Duties: Location: USA Remote Role Mandate:The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products. Candidate Value Proposition:The ideal candidate will collaborate with a team of designers to work on graphics IP development. Role Responsibilities (including but not limited to): Own ASIC IP RTL implementation for IP blocks. Ensure RTL written meets quality checks like Lint/CDC/RDC. Collaborate closely with design team members technical leads and the architecture team to ensure the block meets the power and performance requirements. Collaborate closely with the verification team to develop test plans and review test coverage. Perform IP integration Supervise the RTLtoGDS flow and assist with synthesis and timing closure Work with FPGA engineers to perform early prototyping Support handoff and integration of blocks into larger SOC environments Assist with Algorithm analysis. Performance Measurement:Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics. Must Have Skills: 4 years of experience as a Digital Design Engineer. Recent experience with IP RTL coding within the past 23 years specifically for ASIC (Per CWAM anything beyond would be a challenge) Experience having worked on a design from scratch code from the ground up (outline / provide project work if available) Experience in RTL coding and coding for low power in ASICs Experience in digital design Architecture Strong experience with Verilog and SystemVerilog coding Perl Tcl and Python (or similar) scripting experience NicetoHave Skills: MSEE/CS or equivalent experience Experience developing IP for Graphics Processing Unit (GPU) CPU Compression or Video ASICs experience working on coding for these industries (typically aligns with what this team is doing) Recent track record of projects where individual coded from ground up that were successfully taped out. Soft Skills: Strong verbal and written communication skills
Skills: Location: USA Remote Role Mandate:The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products. Candidate Value Proposition:The ideal candidate will collaborate with a team of designers to work on graphics IP development. Role Responsibilities (including but not limited to): Own ASIC IP RTL implementation for IP blocks. Ensure RTL written meets quality checks like Lint/CDC/RDC. Collaborate closely with design team members technical leads and the architecture team to ensure the block meets the power and performance requirements. Collaborate closely with the verification team to develop test plans and review test coverage. Perform IP integration Supervise the RTLtoGDS flow and assist with synthesis and timing closure Work with FPGA engineers to perform early prototyping Support handoff and integration of blocks into larger SOC environments Assist with Algorithm analysis. Performance Measurement:Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics. Must Have Skills: 4 years of experience as a Digital Design Engineer. Recent experience with IP RTL coding within the past 23 years specifically for ASIC (Per CWAM anything beyond would be a challenge) Experience having worked on a design from scratch code from the ground up (outline / provide project work if available) Experience in RTL coding and coding for low power in ASICs Experience in digital design Architecture Strong experience with Verilog and SystemVerilog coding Perl Tcl and Python (or similar) scripting experience NicetoHave Skills: MSEE/CS or equivalent experience Experience developing IP for Graphics Processing Unit (GPU) CPU Compression or Video ASICs experience working on coding for these industries (typically aligns with what this team is doing) Recent track record of projects where individual coded from ground up that were successfully taped out. Soft Skills: Strong verbal and written communication skills
Education: BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Required Skills: ASICQUALITY CHECKSCODINGFPGATEST PLANS
Additional Skills: VERILOGELECTRICAL ENGINEERINGDIGITAL DESIGNMSEESOCPERLALGORITHMASICSSCRIPTINGMETRICSVALUE PROPOSITIONAPPLICATIONSPECIFIC INTEGRATED CIRCUITFIELD PROGRAMMABLE GATE ARRAYPROTOTYPINGTCLANALOG SILICONPYTHON
Minimum Degree Required: Bachelors Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak Read Write )
Department: Cost of goods sold : 1100
Job Category: IT
Skills: Location: USA Remote Role Mandate:The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products. Candidate Value Proposition:The ideal candidate will collaborate with a team of designers to work on graphics IP development. Role Responsibilities (including but not limited to): Own ASIC IP RTL implementation for IP blocks. Ensure RTL written meets quality checks like Lint/CDC/RDC. Collaborate closely with design team members technical leads and the architecture team to ensure the block meets the power and performance requirements. Collaborate closely with the verification team to develop test plans and review test coverage. Perform IP integration Supervise the RTLtoGDS flow and assist with synthesis and timing closure Work with FPGA engineers to perform early prototyping Support handoff and integration of blocks into larger SOC environments Assist with Algorithm analysis. Performance Measurement:Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics. Must Have Skills: 4 years of experience as a Digital Design Engineer. Recent experience with IP RTL coding within the past 23 years specifically for ASIC (Per CWAM anything beyond would be a challenge) Experience having worked on a design from scratch code from the ground up (outline / provide project work if available) Experience in RTL coding and coding for low power in ASICs Experience in digital design Architecture Strong experience with Verilog and SystemVerilog coding Perl Tcl and Python (or similar) scripting experience NicetoHave Skills: MSEE/CS or equivalent experience Experience developing IP for Graphics Processing Unit (GPU) CPU Compression or Video ASICs experience working on coding for these industries (typically aligns with what this team is doing) Recent track record of projects where individual coded from ground up that were successfully taped out. Soft Skills: Strong verbal and written communication skills
Education: BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Required Skills: ASICQUALITY CHECKSCODINGFPGATEST PLANS
Additional Skills: VERILOGELECTRICAL ENGINEERINGDIGITAL DESIGNMSEESOCPERLALGORITHMASICSSCRIPTINGMETRICSVALUE PROPOSITIONAPPLICATIONSPECIFIC INTEGRATED CIRCUITFIELD PROGRAMMABLE GATE ARRAYPROTOTYPINGTCLANALOG SILICONPYTHON
Minimum Degree Required: Bachelors Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak Read Write )
Department: Cost of goods sold : 1100
Job Category: IT
Employment Type
Full Time
Key Skills
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