Design Verification
Design Verification
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Job Description
Job Description
The candidate will be responsible for writing test plans defining test methodologies developing test benches writing testcases completing functional verification and closing coverage for SoCs/Subsystems
Create System Verilog / UVM verification environment.
Develop tests to meet functional coverage and code coverage requirements defined for the project based on analysis of coverage gaps.
Run regressions debug test failures and file bug report as needed.
Provide verification report as needed to show all implemented tests passing on the RTL.
Required Skills / Experience
Candidate must have minimum 5 years of experience in functional verification
Candidate must have strong knowledge of System Verilog and in UVM methodology
Candidate must have knowledge of AXI AHB protocol
Detailed JD is provided below for DV positions. Ask candidates to provide selfassessment in below table format.
Knowledge/ Skill Area
Selfrating
1 (lowest) to 10 (highest)
System Verilog
UVM
Functional Coverage
Code coverage
Verification Plan Development
Test bench coding (SV UVM)
Test coding simulation debug (SV UVM)
Gate level simulation
AXI Protocol Knowledge
PCIe Gen3 Protocol Knowledge
Gbit Ethernet Protocol Knowledge
USB 3.0 Protocol Knowledge
Employment Type
Full Time
