Design Verification Engineer
Design Verification Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Santa Clara CA
Salary: DOE
Job Description
Skills Required:
- Testbench development System Verilog Universal Methodology (UVM) Python and C tests
- Integration/development of C tests/Application Programming Interface (APIs) and software build flow
- Integration of UVM testbenches
- Test development and debug including without limitation tests for functionality power performance error and connectivity both for RTL and Gate Level Netlist Design Under Test tests for functional and code coverage improvements
- Continuous integration and/or regression testing setup and debug for simulation at both RTL and Gate Level Netlist
- Unified Power Format (UPF) power aware simulation/emulation
- XProp simulation/regression TestBench creation and maintenance
- Coverage collection and closure
- Documentation of tests testbench usecases exclusions and status
Experience Required:
- 7 years to 15 years in Design Verification
UrBench is an equal opportunity employer and is committed to creating a diverse environment. All qualified applicants will receive consideration for employment without regard to race color religion gender gender identity or expression sexual orientation national origin genetics pregnancy status as a parent disability age veteran status or other characteristics as defined by federal state or local laws.
Employment Type
Full Time
