Signal Processing Engineer
Signal Processing Engineer
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Job Description
Signal Processing Engineer for the development of signal processing RTL blocks and their subsequent implementations. We are looking for an individual who is passionate about designing and implementing critical DSP blocks and has experience with ASIC and DSP design.
As a Signal Processing Engineer you will be involved in handson detailed design work where you will contribute to the development of key components used in various communication systems including WiFi BLE GNSS and cellular technologies. You will collaborate with a talented team of engineers to deliver highquality designs that meet industry standards.
About the Role:The Signal Processing Engineer will be responsible for designing developing and optimizing DSPrelated RTL blocks. You will work with various hardware and software tools to verify and validate DSP blocks and ensure they meet the performance criteria. The position involves writing testing and verifying Verilog and System Verilog code for ASIC design and implementation.
In this handson role you will work directly with senior engineers to design state machines data paths arbitration and clock domain crossing logic as well as providing support for logic synthesis and FPGA implementation. You will also ensure that the designs are optimized for low power and high performance and that they meet rigorous testing and verification standards.
Key Responsibilities:- Design & Implementation: Develop signal processing RTL blocks and implement them for various DSP functions. Optimize and finetune DSP blocks for performance and power.
- RTL Design: Use Verilog and System Verilog to write and optimize RTL code for DSP blocks.
- Verification & Testing: Verify the functionality of DSP blocks using test benches and simulation tools. Ensure the RTL is DFTfriendly and can be tested using industrystandard methodologies.
- Design for Test (DFT): Apply your understanding of Design for Test (DFT) principles including scan concepts to improve testability and efficiency of the design.
- Integration & Debugging: Integrate the DSP blocks into larger systems working with other engineers to debug and optimize the overall system functionality.
- Power Estimation: Perform accurate power estimation for RTL blocks and support power optimization during the design phase.
- Collaboration: Work effectively as part of a team providing feedback on designs and supporting others with your expertise in DSP and ASIC design.
- Documentation: Write clear and concise documentation for designs test procedures and verification results. Maintain comprehensive records of design decisions and processes.
- Timing Constraints & Synthesis: Support the logic synthesis process and ensure the RTL code meets timing constraints and passes the synthesis flow.
- Physical Layer Exposure: Exposure to the physical layer of communication chips such as WiFi BLE GNSS or cellular is a plus.
- MS or PhD degree in Electrical Engineering Computer Engineering or a related field with an emphasis in ASIC design and Digital Signal Processing (DSP).
- 5 years of experience in RTL design using Verilog and System Verilog.
- Expertise in developing and optimizing DSPrelated RTL blocks for realtime performance.
- Experience with logic synthesis FPGA implementation and timing constraints.
- Understanding of Design for Test (DFT) concepts including scanbased test techniques and writing DFTfriendly RTL.
- Familiarity with the use of Unified Power Format (UPF) for simulation synthesis and electrical rule checking.
- Experience with equivalence checking and power estimation for RTL blocks.
- Strong communication skills both written and verbal and a collaborative teamoriented mindset.
- Ability to work independently and manage multiple tasks in a fastpaced deadlinedriven environment.
- Experience with physical layer designs in communication chips such as WiFi BLE GNSS or cellular.
- Knowledge of industrystandard simulation and synthesis tools for DSP block verification.
- Familiarity with FPGA and ASIC tools including debugging and timing analysis tools.
- Ability to design state machines data paths arbitration logic and clock domain crossing logic.
- Previous experience with highspeed digital designs and familiarity with related physical layer protocols.
Employment Type
Full Time
