ASIC RTL Design
ASIC RTL Design
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Job Description
Greetings from Maneva!
Job Description
Job Title ASIC RTL Design
Location Bengaluru / Hyderabad / Chennai / Pune / Kochi / Ahmedabad / Noida
Experience 5 15 Years
Work Mode Hybrid
Notice Immediate to 30 Days
Requirements:
Expertise in SoC subsystem/IP design
Expertise in IP design Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI AHB ATB APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
o PCIe
o DDR
o Ethernet
o I2C UART SPI
Expertise in setting up and using tools like
o Spyglass Lint/CDC
o Synopsys DC
o Verdi/Xcellium
Understanding of scripting languages like Make flow Perl shell python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design verification DFT and SW teams on design queries and reviews
If you are excited to grab this opportunity please apply directly or share your CV at and
Employment Type
Full Time
