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You will be updated with latest job alerts via emailSr. Design Verification Engineer
Location: Cupertino CA onsite
Contract
Visa: ANY Visa is fine
3 open Position
Note: Candidate should be local to bay area San Jose CA
Mandatory skills:
DV: Testbench development knowledge System Verilog verification methodologies( UVM) Debugging skills verification planning functional and code coverage Simulation tools(VCS Modelsim or Questa)
Job Description:
Position Overview: We are seeking a talented Design Verification Engineer to join our team. The ideal candidate will focus on verifying complex digital designs and ensuring they meet performance and specification standards.
Key Responsibilities:
Required Skills:
Experience:
Technology Node Experience: 2nm to 14nm
Largest Die Experience:2nm to 14nm
Preferred Qualifications:
If you are passionate about verifying cuttingedge digital designs and ready to contribute to innovative projects we encourage you to apply!
Full Time