Physical Design Architect
Physical Design Architect
Posted on :
23-10-2024
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Job Description
Job Title: Physical Design Architect
Location: San Jose CA. The position is based in California and is a hybrid contract role.
Client: The client operates within the semiconductor domain. Specific client details will be disclosed after the interview process.
Responsibilities:
1. Collaborating closely with the logic design team to define physical architecture and drive physical aspects during the design cycle.
2. Working across various teams including physical design logic design package DFT and test.
3. Performing handson synthesis and PnR using industry standard tools for highspeed digital designs in advanced process nodes.
4. Overseeing all aspects of signoff including power timing physical verification checks and design closure.
Required Experience:
1. 1520 years of experience in Physical Design and timing closure.
2. Handson experience in synthesis PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
3. Experience in multiple large SoC tapeouts in advanced nodes including handson experience in chiplevel physical design and STA closure.
4. Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs expertise in timing closure at block/chip levels and ECO flows.
Location: San Jose CA. The position is based in California and is a hybrid contract role.
Client: The client operates within the semiconductor domain. Specific client details will be disclosed after the interview process.
Responsibilities:
1. Collaborating closely with the logic design team to define physical architecture and drive physical aspects during the design cycle.
2. Working across various teams including physical design logic design package DFT and test.
3. Performing handson synthesis and PnR using industry standard tools for highspeed digital designs in advanced process nodes.
4. Overseeing all aspects of signoff including power timing physical verification checks and design closure.
Required Experience:
1. 1520 years of experience in Physical Design and timing closure.
2. Handson experience in synthesis PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
3. Experience in multiple large SoC tapeouts in advanced nodes including handson experience in chiplevel physical design and STA closure.
4. Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs expertise in timing closure at block/chip levels and ECO flows.
Employment Type
Full Time
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