Post Silicon Validation Engineer
Post Silicon Validation Engineer
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Job Description
Job Title: Post Silicon Validation Engineer
Location: Santa Clara CA
Need candidates who has worked on both Hardware and Software.
Job Description:
Candidates shall have expertise in Post silicon validation bring up and validation of interfaces.
Experience to validate PCIe LPDDR controller/chips for leading edge protocolsesp. DRAM functionality related to configuration tuning and debugging.
Understanding of JEDEC PCIe Standard LPDDR5
PCIe gen4/5 TX/RX validation experience is a must have skill.
Ethernet interface validation and bring up is a must have skill.
Experience in Configuration and tweaking of the registers during bring up and validation.
Experience in validating all the features of DDR memory.
Experience in validating different Ethernet Configuration
Experience in Performance measurement of PCIe Lanes.
Experience in using system debug and handling defects.
Experience in handling debug tools defect management and repo management system is an added advantage.
Employment Type
Full Time
