Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with one or more of the following areas: ASIC power modeling and estimation, defining power targets, power management IP and sensors, peak power management/detection/mitigation, in-rush current, adaptive clock distribution, techniques for power/voltage domains design, and competitive power analysis.
Experience with low power architectures and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
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