Design Lead

Job Title: Design Lead

Location: Plymouth MN

Job Description:

What Youll Be Doing:

• Lead the development of custom radiation hardened DDR3 IP controller and PHY.
• Serve as a point of contact for internal and external DDR IP developmentrelated activities.
• Provide technical leadership and guidance to internal and external development teams.
• Ensure compliance with DDR3 requirements and specifications.
• Maintain deep knowledge of DDR protocols including DMI and apply this knowledge in development.
• Oversee work on logic design Clock Domain Crossing (CDC) solutions and voltage plane optimization.
• Oversee verification processes for DDR IP development Candidate will be using:
• RTL Compiler
• Design Compiler
• ASIC synthesis tools like DC Genus
• FPGA tool platform
• CDC tools

What We Are Looking For:

• 5 Years of experience in ASIC Design
• Experience in DDR IP development
• Familiarity with logic design CDC solutions and voltage plane optimization.
• Familiarity with verification concepts in DDR IP development.
• Familiarity with analog circuit development with a focus on IO circuitry and PHY development.
• Strategic awareness of the competitive landscape for DDR IP.
• Excellent communication and teamwork skills.
• Bachelors or higher degree in Electrical Engineering Computer Science or a related field.
• Radiation effects analysis knowledge/experience
• Advanced node and SOI technology design experience
• Knowledge of OS Linux scripting languages e.g. Perl Shell TCL
• Laboratory experience (hardware configuration measurement systems)

Education:

• Bachelors / Masters