Package Design Engineer

Job Title: Package Design Engineer

Location: Milpitas CA

Job Description:

• The Package substrate design focus on signal and power integrities analyses as well as routing analyses.
• You will be reporting to the Director of Package Design (USA) and working very closely with Package design team in our parent companys headquarters in Japan and Marketing and Engineering teams located in our Milpitas office during pre/post sales process.
• This position requires a broad knowledge of package technology and design.
• Successful candidates will have a deep understanding and experience in the following areas: high performance buildup substrates flip chip assembly or 2.5D packaging.
• Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS and/or ADS tools.

Education:

• Bachelors degree in Electrical Engineering or other semiconductor packaging related discipline
• MS is preferred

Required Experience and Skills:

• 8 to 10 years of experience in semiconductor packaging design modeling extraction and simulations
• Record of success in crossfunctional team environment
• Good experience with Signal and power integrity tools for package level modeling/extraction/simulation
• Ability to work with Package Layout engineers.
• Strong presentation and communication skills

Preferred Experience and Skills:

• Hands on package design; highspeed Signa integrity and Power integrity and package decoupling caps optimizations combined package and PCB Signal integrity and Power integrity Characterizations impedance verification high frequency sparameters extraction Hspice model package Hspice and RLC model extraction and designs
• Hands on highspeed package and PCB design for: highspeed Serdes 112 Gbps PCIeX5 and 6 LPDDR45 Ethernet 25 GBps power aware SI/PI analysis up to 40 GHZ s parameters extraction and verification
• PackagingPCB highspeed interconnections timing analyses eyediagram and jitter budgeting calculation following the LPDDR JEDEC spec or other highsspeed frequency domain sparameters extraction following the base Spec of highspeed interconnect
• Hands on PCB design; SI PI analyses decoupling caps optimizations SI and PI Characterization and extractions impedance verification sparameters verifications with lab measurements Hspice model PCB RLC model extraction and designs
• Packaging routing analyst trace impedance analyses and package layout bump to ball analyses
• Package material characterization frequency dependent model; skin effects smoothness roughness dielectric loss and dielectric constant
• PCB material characterization frequency dependent; routing degree of freedom
• Time domain analyses and jitter budgeting for PCIe2/3/4/5 Serdes 112 GBps Ethernet 25 Gbps LPDDR4/5X MIPI highspeed frequency signaling
• Time domain analyses and budgeting model for LPDDR 3/4/5 LPDDRX 3/4/5/6
• Bathtub curve and BER analyses of high speed signaling
• DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve highspeed interconnections
• Clk jitter analyses routing clk tree analyses
• Simulating multiphysics electrothermal analysis
• Collateral packaging manufacturing and assembly rules
• Chip and package Reliability analyses
• DiePkgpcb PDN model time and frequency Impedance profile AC droop DC drop DC etc.
• IR drop and CPM (chip power model) die model using Redhawk and other tolls
• Core PI: simulation capability tool/flow and past experience on measurement capability lab tool set up.