STAStatic Timing Analysis Synthesis

Hope youre doing well!!

We are hiring for the STA Synthesis role. Please find the JD below

JOB Designation: STA Synthesis

JOB Location: PAN India

Mode of Hiring: Fulltime FTE

Notice Period: Immediate to 60 days

Experience:310 years

Required Skills:

We seek bright ASIC design engineers with excellent analytical and technical skills. This is a fantastic opportunity to be part of a fastpaced team responsible for delivering Snapdragon CPU design and flows for highperformance SoCs in sub10nm process for Mobile Compute and IOT market space.

• Development of ASICs with emphasis in Static Timing Analysis (STA) Power Distribution Network (PDN) Analysis Power Estimation Place and Route Low Power Implementation
• RTL design Synthesis Place and Route Implementation low power Thermal analysis and Power estimation teams to optimize Performance Power and Area (PPA) for HighSpeed CPU Cores and Sub System
• Highperformance CPU STA Timing closure and ASIC design Implementation work experience
• Perl/TCL Python and C skills are needed
• Strong problemsolving and ASIC development/debugging skills
• Experience with CPU microarchitecture and their critical path
• Lowpower implementation techniques experience
• Highspeed CPU implementation
• Clock Tree Implementation Techniques for HighSpeed Design Implementation are required
• Exposure to Constraint management tools and Verilog coding experience.

If anyone is interested please send an updated CV to