Explore trade-space of potential FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (S) vs. performance
Implement FPGA with latest design practices and tools from block-level microarchitecture and through HDL coding
Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensurethe design is completed on schedule
Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards
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