Electrical Validation Post Silicon Validation

Hello

Hope you are doing great.

This mail is in regards to a career opportunity with one of our clients we are currently looking for professionals with the below experience.

Role Electrical Validation Post Silicon Validation

Location: Santa Clara CA (Onsite)

Duration: Contract

Skills:

• Need Hardware Engineers who have highspeed interface (DDR5/PCIe Gen 5) experience.
• Candidates with Silicon Validation experience with Electrical background and Python scripting will be a plus.
• Candidates with 3 to 5 years experience as well but they should be strong in highspeed basics.
• FPGA/Software/Functional Validation candidates are not relevant for this requirement.

Skills Required

Experience in Post Silicon Electrical Validation of server processors (if server processor is too specific you can remove server)

High speed communication principles circuits and signal integrity principles

Computer architecture knowledge

DRAM architecture (up to (DDR5) PCIe (Gen 5) architecture knowledge

Die Interconnect Buses and other GPIO (I2C SPI I3C HSuART etc)

SW skill for test plan and test automation Python knowledge is a plus

Statistical principles for data analysis

System level test with margin analysis experience is a plus.

Job Description:

Silicon validation experience preferably in the area of SERDES DDR or highspeed interface design.

Experience to validate PCIe CXL DDRx LPDDR controller/chips for leading edge protocols and advanced nodes.

Understanding of JEDEC PCIe Standard

Experience in PCIe TX/RX Validation

Knowledge on MRC algorithm and tuning for DDR memories

Bring up characterization and validation of Silicon.

Experience in system marginality validation

Work with design team to debug problems and performance issues. Report results to design teams.

Support customer silicon bring up and post silicon queries of IP and help to debug customer issues with same. Debug issues with SOC IP and boards as needed.

Execute test requests from design team or customers to measure specific parameters or root cause issues.

Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced and minimize any silicon issues

Good understanding of lab equipment and measurement techniques for highspeed interfaces. High speed scopes probes spectrum analyzers BERTs.

Knowledge of board and package design signal integrity and power integrity a plus

Knowledge of DDR trainings and memory system operation a plus

Software proficiency for python test scripting data handling and reporting

Laboratory experience including handson use of equipment: oscilloscope logic analyzer etc.

Excellent problemsolving skills good communication skills and ability to work in a team environment

Work with design team to understand requirements fashion tests and review results