Founded in 2019 by Philippe Notton and financed by the European Union SiPearl embodies Europes dream of mastering the technological heart of its supercomputers: the microprocessor.
Since our creation in 2019 we host 170 collaborators in 6 offices: France (MaisonsLaffitte Massy Grenoble Sophia Antipolis) Germany (Duisburg) Spain (Barcelona).
After a successful series A in 2023 (90M ) SiPearl has recently won an emblematic contract to equip Europes first exascale supercomputer JUPITER who will be operated by the EuroHPCs center of research from Jlich (Germany). And as the dream of a European machine crossing the 1 billion billion mark calculations per second thanks to an European microprocessor is becoming reality SiPearl is willing to hire 150 engineers by the end of 2024!
What a regular day at the job might look like:
Define & document complex hardware architecture on SoC level like core interconnect memory and interface components. Write specifications such as HAS (high level architecture specification) and MAS (micro architecture specification)
Define roadmaps on SoC and block level
Determine the product architecture for SoCs and multidie SiPs in close cooperation with marketing key customers and R&D teams for HW and SW.
Define and manage requirements on platform SoC and blocklevel
Investigate architectural tradeoffs to optimize performance powerconsumption silicon area and platform BOM
Define detailed integration concepts for complex IP blocks evaluate internal and external IP
Define and document of KPIs on system level as well as on block level
Support the analysis of KPIs via architectural modelling
Closely collaborate with the development teams for design verification and platform development e.g. form and lead cross functional team
What would make you succeed in this role:
Graduate from an engineer school or from a Master ( 5 years diploma post baccalaurat
A first accomplished experience of 1 year minimum preferably in the micro electronics sector.
Drawn to this type of function in high added value tech sectors.You are ready to be involved in the blooming development of a human size organization.
At least 4 years of digital HDL design or integration
At least 2 years of digital design verification using SystemVerilog
Senior experience of coveragebased verification and use of verification IPs.
Experience of using verification management tools.
Experience of using external verification resources.
(Preferred) Experience of team building
(Optional) Experience of AMBA and Arm IP designs
Someone adaptable
Autonomous
Excellent oral and writing English communication.
Recruitment process
Discovery interview with our Talent Acquisition Partner (30)
Personality test no need to worry there is no wrong or right answer; our goal is to get to see beyond your resume (45)
Technical interview (1h)
Interview with your future manager (1h)
Benefits and conditions:
Contract:CDI
Benefits: meal vouchers (Sodexo) health insurance (70% covered by SiPearl) 8 to 9 RTTs 5 days per year of remote work from any EU location
Work model: OnSite/Hybrid (2 days remote)
Location: Grenoble Duisburg MaisonsLaffitte
Awesome activities such as: Hackathons Training Challenges Quarterly Kickoff sessions team events Company events and much more
Are you curious to learn more about us
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At SiPearl we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit experience and alignment with our companys goals and values.
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