Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, etc.).
Experience in scripting using Python, Perl, or shell scripts.
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