To be part of a highly skilled ASIC Team working on the newest technology nodes
Responsible for overall IP and subsystem verification from test plan creation UVM development to signoff
Ensure first pass product through multidimensional verification coverage including mixed mode verification
Mentoring and coaching junior team members
Pair with similar domain specialists across other geographical locations on core technical initiatives
SKILLS required
Strong knowledge of SERDES/UNIPRO/PCIE/UFS protocols
Exposure to verification of complex high speed PHY and/or complex AMS IPs
Proven track record of building testplan UVM environment and testbenches
Experience with RTL debugging score boarding and code coverage analysis
Sound knowledge of System Verilog and UVM Methodology
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
MS/MTech BS/BE (Electronics)
Experience Required Years
Pls send your resume to