Digital Design / Verification Engineer

Position Name:Digital Design / Verification Engineer

Responsibilities:

Principal Accountabilities:

• Be responsible for complete system level (analog + digital + external components) verification
• Implement simulation test benches/tests that verify the product’s usage scenarios
• Communicate with analog and digital designers to resolve issues found during verification

Key Performance Measures:

• First-time-right functional silicon according to specification
• Balance the trade-off between target verification coverage and verification effort
• Functional equivalence of models to schematics, simulation performance of models Ensuring accordance with corporate rules and guidelines

Qualifications:

• 7+ years of experience in Mixed-signal or System level IC verification
• Engineering degree or above in Electronics or equivalent education.
• Experience with Virtuoso
• Experience with mixed-mode verification. Bench creation, making scenarios, bug reporting, and cooperated with a designer to fix
• Experience with creating and using real-numbered models in SystemVerilog or analog behavioral models in Verilog-A/MS
• Familiarity with Linux operation, and scripting languages like Makefile, Perl, Tcl, or Python
• Experience in UVM-based verification flow is a plus
• Experience with circuit design is a plus
• Strong interpersonal, communication, and organizational skills
• Collaborate with the design team for an efficient verification method
• Good English language skills written + oral.

About Company

This company is one of the cores of technological innovation centers and attracts top engineers from all over the world. We have many companies and offices in Japan, offering various engineering and corporate roles.Our mission is to makelives easier and a world that's safer, healthier, greener, and smarter.