Sr. Design Verification Engineer

Sr. Design Verification Engineer

Location: Bay Area, CA ( OR Remote Anywhere)
Experience level: 7+ Years
Type: 12 month Contract

Responsibilities:

Must be a quick learner, independent and communicate well.

Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms
Building a testbench for a medium complexity block using System Verilog and UVM

Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.

Developing, maintaining and supporting the UVM verification environment.

Debugging tests with design engineers to deliver functionally correct design blocks

OOPS, randomization, constraints, interfaces

Writing & analyzing functional coverage, assertions

Generating and analyzing code coverage & writing waivers

Skills:

Must have Skills:

• SV-UVM : Expert
• Coverage Driven Verif: Expert
• Scripting (Python3/Bash/Tcl): Intermediate
• Fixed point Arithmetic: Intermediate
• Floating Point Arithmetic: Intermediate
• PCIe: Intermediate

EDUCATION: Bachelor's degree in Computer Science or related field or equivalent combination of industry-related professional experience and education.