2x FPGA Engineers (1x Altera, 1x Xilinix)
Quick summary of skillsets for both FO spots:
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Demonstrated experience with FPGA design using VHDL
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Transceiver design experience for high-speed/bandwidth interfaces (e.g. SERDES, Ethernet, PCIe, JESD etc.)
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FPGA design experience with large data manipulation / throughput (e.g. FIFOs, BRAM, streaming-to-memory map, etc.)
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Strong understanding of clock-domain-crossing, timing constraints
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System Verilog for Verification
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Familiarity with Linux OS, Make files
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Local to SD, onsite support for Lab debug, familiar with Lab debug strategies (e.g. scopes, ILAs, etc.)
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Familiar and/or experience with Mathworks Simulink HDL Coder
FO for Altera:
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Recent experience with Altera Quartus tool flow
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Familiar with Quartus SignalTap for FPGA debug
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Familiar with Avalon Bus Interface
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Design experience with Arria, Cyclone devices
FO for Xilinx:
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Recent experiance with Xilinx Vivado tool flow
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Familiar with Xilinx debug cores (ILA, VIO, IBERT)
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Familiar with AXI Bus Interface
Familiar and/or design experience with MPSoC devices