Design Verification Engineer - 30607

Job Description

• BS/MS in EE/EC with 7 years of relevant experience in the verification of IP cores and/or SOC
• Must have proven experience in developing HVL (System Verilog/UVM) based test environments developing and implementing test plans implementing and extracting verification metrics such as functional coverage and Code coverage.
• Experience on DDR Protocol is necessary. Understanding of BIST would be added advantage.
• Exposure to IP design and verification processes including VIP development is an added advantage.
• Good communication skills debug and problem solving skills and should be self motivated

Education/Experience

• Be a technical contributor in the Verification Tasks &ndash System Verilog/Verilog coding of testbenches Test cases performing verification tasks such as coverage debug regressions using the latest methodologies such as UVM.
• Creates deliverables which do not require close review or supervision by a Senior Technical Engineer
• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment at least for small/ medium complexity features of the protocol/ product specs
• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable
• Works in a project and team oriented environment with teams spread across multiple sites worldwide.

Job Summary

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About the Recruiter/Company

• Company/Recruiter Name: Recruitment Specialist Diksha Jhala
• Details: This is Diksha Jhala working with Zigsaw as a Recruitment Specialist. I specialise in recruitment for .net React Native & Flutter roles roles at Zigsaw. If you are looking for Jobs in the above domain OR for any query related to the above Job kindly reach to me on Call and WhatsApp atOR Email your resume at

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